CMOS Circuit Builder: Practice Transistor-Level Design
Reading a finished CMOS circuit is one skill; building one from a bare Boolean expression is a different, harder skill, and it is the one most digital electronics exams actually test. The CMOS Builder gives you a randomly generated expression and asks you to construct the pull-up and pull-down transistor networks yourself, entering your answer in standard series (·) and parallel (+) notation, then checks it instantly against the correct implementation.
It is designed as active practice rather than a reference tool: you commit to an answer before seeing whether it is right, which is closer to exam conditions than passively reading a generated circuit. Difficulty scales with the number of variables in the expression, so you can start with simple two-input gates and work up to the multi-term AND-OR-INVERT functions typical of final exams and VLSI coursework.
- = series, // = parallel- = series, // = parallelPUN/PDN theory explained, plus tips for getting it right
Pull-Up and Pull-Down Networks Explained
Every static CMOS gate is built from two complementary halves. The PDN connects the output to ground and is built from NMOS transistors: series NMOS implements AND behaviour, parallel NMOS implements OR. The PUN connects the output to VDD and is built from PMOS transistors arranged as the dual of the PDN: wherever the PDN uses series, the PUN uses parallel, and vice versa. Because both networks are driven by the same inputs, exactly one of them conducts for any input combination, which is why CMOS gates consume almost no static power.
One important consequence: a natural CMOS gate is always inverting. A single CMOS stage can implement NAND, NOR, or any AND-OR-INVERT function directly, but a plain AND or OR needs an extra inverter stage on the output. The Builder includes an output-inverter option for exactly this reason.
Tips for Getting It Right
- Start with the PDN: implement the complement of the function using NMOS (series = AND, parallel = OR)
- Derive the PUN as the exact dual of your PDN: swap series and parallel
- Check whether the target expression is inverting; if not, you need the output inverter
- Verify with a quick truth-table check: try one input combination and trace which network conducts
- Stuck? Use the CMOS Generator to see the correct circuit for any expression, then come back and practice