Digital Logic Quiz: Read CMOS Circuits, Not Just Draw Them

Most practice in a digital electronics course goes one direction: given a Boolean expression, draw the circuit. This quiz runs the exercise in reverse: you are shown a finished CMOS transistor network and have to work out which Boolean expression it implements. That reverse skill is what separates students who have memorised a few gate shapes from students who genuinely understand how series and parallel transistor arrangements encode AND, OR, and inversion, and it is exactly the kind of question that shows up on exams precisely because it cannot be answered by memorisation alone.

Practice Quizzes

Pick a difficulty. You’ll see a CMOS circuit and choose the matching Boolean expression.

Easy

2 variables (A, B)

Medium

3-4 variables (A-D)

Hard

5-6 variables (A-F)

How to read a CMOS circuit, and choosing a difficulty

How to Read a CMOS Circuit

Look at the PDN first (NMOS transistors between output and ground): series transistors mean AND, parallel transistors mean OR
The PDN implements the complement of the output: if the PDN conducts when A AND B are high, the gate is a NAND
Check for an output inverter stage: it flips an inverting gate (NAND, NOR) into its non-inverting form (AND, OR)
Confirm with the PUN: it should always be the series/parallel dual of the PDN
When two options look similar, pick one input combination and mentally evaluate both. Only one will match the circuit

Choosing a Difficulty

Easy uses 2 variables and maps to single-gate circuits (NAND, NOR, AND, OR). Start here if you are still learning series/parallel network rules. Medium uses 3-4 variables with compound AND-OR structures, matching typical mid-term exam questions. Hard uses 5-6 variables and mirrors the complex AND-OR-INVERT functions found in final exams and VLSI course problem sets. Questions are generated dynamically, so you get a fresh circuit every time. Practice until reading transistor networks feels automatic. If you want to study a specific circuit first, build it in the CMOS Generator and examine how each part of the expression maps to the transistor layout.