What is a CMOS circuit simulator?

A CMOS circuit simulator converts Boolean expressions into visual logic circuit diagrams using CMOS (Complementary Metal-Oxide-Semiconductor) technology. It is widely used by EEE and digital electronics students to visualize combinational logic circuits without needing physical hardware or expensive software.

How do I convert a Boolean expression to a logic circuit diagram?

Enter your Boolean expression (e.g. A AND B OR NOT C, or SOP/POS forms) into Logic Gate Simulator and click Generate. The tool instantly draws the full logic circuit diagram and generates the complete truth table — useful for digital electronics assignments and EEE coursework.

Can I use this for EEE coursework and digital electronics assignments?

Yes. This tool is designed for EEE students studying digital logic design, Boolean algebra, and CMOS circuits. It helps you verify Boolean expressions, draw logic gate diagrams, and check truth tables for combinational circuits — all common tasks in digital electronics courses.

Is this logic gate simulator free to use?

Yes, completely free. No account, no login, no download required. Works entirely in your browser — ideal for students who need a quick tool during revision or lab sessions.

What logic gates are supported?

AND, OR, NOT, NAND, NOR, XOR, and XNOR gates are all supported. You can combine them with parentheses to build complex combinational circuits — including sum-of-products (SOP) and product-of-sums (POS) expressions commonly used in digital logic design.

What is the difference between NAND and NOR gates in CMOS design?

In CMOS design, NAND gates use series NMOS and parallel PMOS transistors, while NOR gates use parallel NMOS and series PMOS. NAND gates are preferred in CMOS because series NMOS transistors are faster than series PMOS, making NAND implementations more efficient. This simulator lets you visualise both instantly.

NAND Gates, NOR Gates, and SOP vs POS Explained

NAND, NOR, and the choice between Sum of Products (SOP) and Product of Sums (POS) forms are three of the most exam-tested topics in a first digital electronics or EEE coursework module, and three of the most commonly confused. This page covers the truth tables, the CMOS transistor-level design of each gate, and how to convert a truth table into either canonical form, with worked examples you can open directly in the CMOS Generator.

What Is a NAND Gate?

NAND is short for NOT AND. A NAND gate outputs LOW (0) only when every input is HIGH (1); for any other input combination the output is HIGH. For two inputs A and B, the Boolean expression is Y = NOT (A AND B), written as Y = (A·B)'.

A	B	Y = NOT(A AND B)
0	0	1
0	1	1
1	0	1
1	1	0

CMOS Implementation of a NAND Gate

A two-input CMOS NAND gate uses four transistors, split into the two complementary networks every static CMOS gate is built from: the pull-down network (PDN) and the pull-up network (PUN).

PDN (NMOS, series): two NMOS transistors in series between the output and ground. Both A and B must be HIGH to turn on both transistors and pull the output LOW, which directly implements the AND condition for the pull-down path.
PUN (PMOS, parallel): two PMOS transistors in parallel between VDD and the output. Either A or B being LOW turns on its PMOS transistor and pulls the output HIGH: the dual of the series PDN, exactly as the PUN/PDN duality rule requires.

Because the PUN is always the exact dual of the PDN, exactly one network conducts for any input combination, which is why static CMOS gates draw almost no current except while switching. You can practice building this exact PUN/PDN pair by hand in the CMOS Builder.

Why NAND Is Called a "Universal Gate"

Any Boolean function can be built using only NAND gates. A single NAND gate with its two inputs tied together behaves as a NOT gate; two NAND gates in sequence recreate an AND gate; three arranged correctly recreate an OR gate. Because NAND (and, separately, NOR) can express the entire Boolean operator set, standard-cell chip libraries are often built almost entirely from NAND cells, which simplifies manufacturing and characterization.

Why CMOS Designers Prefer NAND Over a Plain AND Gate

A plain AND gate needs a NAND stage followed by a separate inverter, three extra transistors and an extra stage of delay. Since NAND is a single inverting stage, it is faster and cheaper in transistors, which is why digital designs favor NAND (and NOR) gates as building blocks and treat AND/OR as NAND/NOR plus an inverter.

What Is a NOR Gate?

NOR is short for NOT OR. A NOR gate outputs HIGH (1) only when every input is LOW (0); if any input is HIGH, the output is LOW. For two inputs A and B, the Boolean expression is Y = NOT (A OR B), written as Y = (A+B)'.

A	B	Y = NOT(A OR B)
0	0	1
0	1	0
1	0	0
1	1	0

CMOS Implementation of a NOR Gate

NOR is the exact electrical dual of NAND:

PDN (NMOS, parallel): two NMOS transistors in parallel. Either A or B being HIGH turns on its NMOS transistor and pulls the output LOW: the OR condition.
PUN (PMOS, series): two PMOS transistors in series. Both A and B must be LOW to turn on both PMOS transistors and pull the output HIGH.

NAND vs NOR in CMOS: Why NAND Usually Wins

Both gates are universal and both are single-stage inverting gates, but they are not interchangeable in practice. NAND's series transistors in the PDN are NMOS, and electron mobility in silicon is roughly 2 to 3 times higher than hole mobility, which drives the PMOS transistors. NOR's series transistors in the PUN are PMOS, the slower carrier type, so a series-connected NOR gate has higher resistance and worse propagation delay than an equivalently sized NAND gate. This is the main reason NAND-based standard cells dominate over NOR-based ones in most digital logic, even though both are functionally universal.

	PDN (pull-down)	PUN (pull-up)
NAND	NMOS, series	PMOS, parallel
NOR	NMOS, parallel	PMOS, series

NOR gates are still important where their structure fits the application directly, for example NOR-based ROM and PLA memory arrays, where the parallel pull-down naturally implements a wired-OR across many inputs. Practice constructing both PUN/PDN pairs yourself in the CMOS Builder, or generate either gate instantly in the CMOS Generator.

Sum of Products (SOP) vs Product of Sums (POS)

SOP and POS are the two canonical ways to write any Boolean function directly from its truth table, and every digital logic course expects you to be able to derive both.

Sum of Products (SOP): an OR ("sum") of AND ("product") terms, e.g. Y = A·B + A'·C. Built from one minterm (a product term covering exactly one row) for every row where the output is 1.
Product of Sums (POS): an AND ("product") of OR ("sum") terms, e.g. Y = (A+B)·(A'+C). Built from one maxterm (a sum term covering exactly one row) for every row where the output is 0.

Worked Example

Take this 2-variable truth table:

A	B	Y
0	0	0
0	1	1
1	0	0
1	1	1

SOP (sum of the minterms where Y = 1, rows 2 and 4): Y = A'·B + A·B, which simplifies to Y = B.

POS (product of the maxterms where Y = 0, rows 1 and 3): Y = (A+B)·(A'+B), which also simplifies to Y = B; both canonical forms always describe the same function, just derived from opposite sides of the truth table.

Which Form Should You Use?

As a rule of thumb, SOP is more compact when the truth table has more 1s than 0s (fewer minterms to sum), and POS is more compact when there are more 0s than 1s (fewer maxterms to multiply). The two forms also map directly onto gate structure: SOP implements naturally as an AND-OR network, which by De Morgan's theorem becomes an all-NAND ("NAND-NAND") circuit in CMOS. POS implements as an OR-AND network, which becomes an all-NOR ("NOR-NOR") circuit, tying directly back to why the NAND and NOR gates above are the building blocks CMOS synthesis tools reach for first.

Type either an SOP or POS expression straight into the CMOS Generator to see its circuit diagram and verify the truth table, or test yourself on reading circuits back into Boolean form in the practice quizzes.

Frequently Asked Questions

Why is a NAND gate faster than a NOR gate in CMOS?

NAND’s series transistors are NMOS, driven by electrons, which have higher mobility in silicon than the holes driving PMOS. NOR’s series transistors are PMOS, the slower carrier type, giving it higher resistance and worse propagation delay at equivalent transistor sizing.

Can every Boolean function really be built from NAND gates alone?

Yes. NAND is functionally complete: tying both inputs of a NAND gate together makes a NOT gate, and NOT plus NAND can recreate AND, OR, NOR, and XOR. This is why NAND-only standard-cell libraries are common in chip design.

How do I convert a truth table into an SOP expression?

Write one product (AND) term for every row where the output is 1, using the variable itself when it is 1 in that row and its complement when it is 0, then OR all those terms together.

Is a NAND-NAND circuit the same as an SOP implementation?

Yes. An SOP expression implemented as AND gates feeding an OR gate is logically identical to replacing every gate with a NAND gate (an AND-OR network and a NAND-NAND network compute the same function by De Morgan’s theorem), and the NAND-NAND version uses fewer transistors in CMOS.

Do I need to simplify an SOP or POS expression before building the CMOS circuit?

No, the CMOS Generator accepts unsimplified expressions directly. Simplifying first (for example with a Karnaugh map) produces a smaller circuit with fewer transistors, but is a separate step from the SOP/POS derivation itself.