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The CMOS Inverter

By Han · Published 21 September 2026

The inverter is the simplest logic gate and the natural place to start understanding CMOS, because every more complex gate is built on the same principle. A CMOS inverter uses just two transistors: one PMOS transistor connected between the positive supply V_DD and the output, and one NMOS transistor connected between the output and ground. The input drives both gates at once, and the output is taken from the point where the two transistors meet. The word complementary in CMOS refers exactly to this arrangement of a matched pair that behave in opposite ways.

Understanding the inverter means understanding two things: how it produces a clean logic 0 or 1 (its static behaviour, captured by the voltage transfer characteristic), and how much power it costs to run. Both are covered below. If you want to see the inverter inside larger circuits, the CMOS gate design guide extends the same pull-up and pull-down idea to any Boolean function.

How it switches

An NMOS transistor turns on when its gate voltage is high; a PMOS transistor turns on when its gate voltage is low. Because both gates share the same input, exactly one transistor is strongly on at a time in steady state.

Input low (0): the NMOS is off and the PMOS is on. The PMOS connects the output to V_DD, so the output is pulled to a solid logic 1.
Input high (1): the NMOS is on and the PMOS is off. The NMOS connects the output to ground, so the output is pulled to a solid logic 0.

The output is always the complement of the input, which is the whole point of an inverter. Just as importantly, in either steady state there is no continuous path from V_DD to ground, because one of the two transistors is always off. This is the structural reason CMOS draws almost no current when it is not switching, and it is what let CMOS displace the older NMOS-only logic families that wasted power constantly.

The voltage transfer characteristic

The voltage transfer characteristic, or VTC, is the plot of output voltage against input voltage as the input sweeps slowly from 0 to V_DD. It is the single most informative graph for a logic gate, and for the CMOS inverter it has a distinctive steep, almost vertical, transition in the middle. That steepness is what gives digital logic its noise immunity: a small change in a valid input voltage produces almost no change in the output.

The curve is traditionally divided into five regions as the input rises:

Region 1: input near 0. NMOS off, PMOS in its linear region, output held at V_DD.
Region 2: input rising past the NMOS threshold. NMOS enters saturation, PMOS still in linear region, output begins to fall.
Region 3: the transition. Both transistors are in saturation, the output drops steeply, and this is the only region where a direct current path briefly exists.
Region 4: NMOS now in linear region, PMOS in saturation, output continues down toward 0.
Region 5: input near V_DD. PMOS off, NMOS in linear region, output held at 0.

The input voltage at which output equals input, in the middle of Region 3, is the switching threshold V_M. By sizing the PMOS wider than the NMOS to compensate for the lower mobility of holes, a designer can place V_M at roughly V_DD/2, which gives the most symmetric and robust behaviour.

Noise margins

Real signals pick up noise on the way from one gate to the next, so a gate has to tolerate inputs that are not exactly 0 or V_DD. Noise margins quantify that tolerance. They are defined using the two points on the VTC where its slope equals -1, which mark the edges of the usable logic levels:

V_IL: the highest input still guaranteed to read as logic 0.
V_IH: the lowest input still guaranteed to read as logic 1.
V_OL and V_OH: the output voltages for logic 0 and logic 1, which for CMOS are very close to 0 and V_DD.

From these, the low and high noise margins are NM_L = V_IL - V_OL and NM_H = V_OH - V_IH. A larger noise margin means more unwanted voltage can be added to a signal before the next gate misreads it. Because CMOS outputs swing nearly rail to rail, its noise margins are large, typically a good fraction of V_DD, which is another reason the family is so dependable.

Power: static versus dynamic

CMOS power comes in two kinds. Static power is what the gate burns while sitting still. Since one transistor is always off in steady state, the only static current is a tiny leakage, so static power is very small (though it has grown in importance as transistors have shrunk).

Dynamic power is what dominates in classic CMOS, and it is spent charging and discharging the load capacitance every time the output switches. It follows P_dyn = α C V_DD² f, where C is the load capacitance, f the clock frequency, and α the activity factor (the fraction of cycles on which the output actually toggles). The square dependence on V_DD is the reason lowering the supply voltage is the most effective single lever for cutting power, and it is why supply voltages have fallen steadily across chip generations. A smaller contribution comes from the brief short-circuit current during Region 3 of each transition, when both transistors conduct at once.

Frequently Asked Questions

How many transistors are in a CMOS inverter?

Two: one PMOS transistor between the supply and the output, and one NMOS transistor between the output and ground, with both gates driven by the same input.

Why does a CMOS inverter use almost no static power?

In either steady state one of the two transistors is off, so there is no continuous conducting path from the supply to ground. Only a small leakage current flows, so static power is very low.

What is the switching threshold of a CMOS inverter?

It is the input voltage at which the output equals the input, in the middle of the transfer curve. Sizing the PMOS wider than the NMOS places it near VDD/2 for symmetric behaviour.

Why is the PMOS made wider than the NMOS?

Holes have lower mobility than electrons, so a PMOS transistor conducts less current than an NMOS of the same size. Making the PMOS wider balances the pull-up and pull-down strengths.

What causes dynamic power in CMOS?

Charging and discharging the load capacitance on every output transition, following P = alpha C VDD squared f. A smaller short-circuit current during each transition adds a little more.

Keep learning

Designing a CMOS gate from a Boolean expression, which generalises the inverter to any function.
NAND, NOR and SOP vs POS for the pull-up and pull-down networks of real gates.
Logic gates explained for the logical behaviour these transistors implement.
See transistor-level circuits for any expression in the CMOS Generator.

References: A. S. Sedra and K. C. Smith, Microelectronic Circuits; J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits: A Design Perspective; N. Weste and D. Harris, CMOS VLSI Design.