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How to Design a CMOS Gate from a Boolean Expression

By Han · Published 21 September 2026

Once you understand the CMOS inverter, the same idea scales up to any logic function. Every static CMOS gate is made of two complementary networks: a pull-down network (PDN) of NMOS transistors that connects the output to ground, and a pull-up network (PUN) of PMOS transistors that connects the output to V_DD. For any input combination, exactly one network conducts, so the output is always driven firmly to 0 or to 1 and never left floating.

A single static CMOS gate is naturally inverting. The transistors can only pull the output to a value, they cannot pass the true input signal through, so a gate always implements a function of the form Y = f(inputs)'. That is why NAND and NOR (and their compound cousins) come for free, while AND and OR need an extra inverter stage. This page gives the recipe and works a full example you can reproduce in the CMOS Generator.

The two rules that do all the work

Building the pull-down network is where you start, because NMOS transistors pull toward ground and the gate output goes low exactly when the inner function is true. Two rules map Boolean structure onto transistor topology:

AND becomes series. Transistors in series conduct only when all of them are on, which matches the AND condition.
OR becomes parallel. Transistors in parallel conduct when any one of them is on, which matches the OR condition.

The pull-up network is then the dual of the pull-down network, built from PMOS transistors. Wherever the PDN has transistors in series, the PUN has them in parallel, and wherever the PDN has them in parallel, the PUN has them in series. Because PMOS turns on with a low gate voltage, this dual structure conducts for exactly the input combinations the PDN does not, which is what guarantees one and only one network is ever on. Both networks are driven by the same, uncomplemented, input signals.

The design procedure

Write the function in inverting form, Y = f(inputs)'. If your target function is non-inverting, such as AND, design the inverting version (NAND) and add an output inverter.
Look at the inner function f. Build the NMOS pull-down network from it directly, turning each AND into a series connection and each OR into a parallel connection.
Build the PMOS pull-up network as the exact dual of the pull-down network, swapping every series for parallel and every parallel for series.
Connect the pull-down network between the output and ground, the pull-up network between V_DD and the output, and drive every gate with its input.
Count transistors as a sanity check: a gate with N literals in f uses N NMOS plus N PMOS, so 2N transistors in total.

Worked example: an AND-OR-invert gate

Consider Y = (A·B + C)'. The inner function is f = A·B + C, an AND term ORed with a single variable. This is a compound gate, sometimes called an AND-OR-invert (AOI) gate, and building it as one static CMOS gate is far cheaper than wiring together separate AND, OR, and NOT gates.

Pull-down network (NMOS). Read f directly:

A·B is an AND, so transistor A is in series with transistor B.
That series pair is ORed with C, so the whole A-B branch is in parallel with transistor C.

Pull-up network (PMOS), the dual. Swap series for parallel and parallel for series:

A and B, which were in series in the PDN, go in parallel in the PUN.
That parallel pair, which was in parallel with C in the PDN, goes in series with C in the PUN.

The finished gate uses three NMOS and three PMOS transistors, six in total, for a function that would otherwise take an AND gate, an OR gate, and an inverter. Check the behaviour: when A and B are both high, or when C is high, the pull-down network conducts and pulls Y low, exactly matching Y = (AB + C)'. Enter NOT ((A AND B) OR C) in the CMOS Generator to see this circuit drawn out, or build the series and parallel branches yourself in the CMOS Builder.

Why designers reach for compound gates

The AOI structure above generalises. Any Sum of Products expression, once complemented, becomes a single AND-OR-invert gate, and any Product of Sums expression becomes an OR-AND-invert (OAI) gate. Building these as one compound static gate rather than as a cascade of primitive gates saves both transistors and, because there is only one stage of switching, propagation delay. This is the practical reason the SOP and POS canonical forms map so neatly onto CMOS, and why synthesis tools favour them.

One caution worth remembering: long series chains are slow. Stacking many NMOS transistors in series (or many PMOS, which is worse because holes are slower) raises the resistance of that path and degrades the gate's delay, so in practice a designer limits how deep a series stack gets and breaks very wide functions across several gates. The trade-off between transistor count and speed is a recurring theme once you move from textbook gates to real standard-cell libraries.

Frequently Asked Questions

Why can a single static CMOS gate only implement inverting functions?

The transistor networks can only pull the output to ground or to the supply, not pass an input through unchanged. That built-in inversion means one gate naturally realises Y = f prime, so AND and OR each need an added inverter.

How do I build the pull-down network from a Boolean expression?

Take the inner function f and translate its structure directly: every AND becomes NMOS transistors in series, and every OR becomes NMOS transistors in parallel.

What is the relationship between the pull-up and pull-down networks?

They are duals. Wherever the pull-down network has transistors in series the pull-up has them in parallel, and vice versa, so exactly one network conducts for any input.

How many transistors does a CMOS gate need?

A function with N literals needs N NMOS transistors in the pull-down network and N PMOS in the pull-up network, giving 2N transistors in total.

What is an AND-OR-invert gate?

An AOI gate implements the complement of a Sum of Products expression, such as (AB + C) prime, as a single compound static CMOS gate, which is cheaper and faster than separate AND, OR, and NOT gates.

Keep learning

The CMOS inverter, the two-transistor case this method generalises.
NAND, NOR and SOP vs POS for the pull-up and pull-down networks of the basic gates.
De Morgan's theorem, which puts any function into the inverting form this method needs.
Generate the circuit for any expression in the CMOS Generator, or build it by hand in the CMOS Builder.

References: N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective; J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits.